The present invention relates to the design of semiconductor chips such as RF switches.
CMOS device performance is affected, often critically, by dimension control of the device""s gate length. A manufacturable gate definition process includes both gate patterning and etching. For example, while it is generally desirable to use as little polysilicon as possible in the formation of the gates of RF CMOS devices, the typical polysilicon etch process used in the formation of such CMOS devices requires the use of more polysilicon than is desired for these gates.
That is, gate etching is sensitive to the xe2x80x9cmicro-loadingxe2x80x9d effect. Micro-loading is usually defined as the utilization of the chip area between the gate and the chip. Micro-loading is generally not a concern for typical LSI circuits which have ratios of 10% or more of gate area to total chip area. However, for certain types of applications, such as RF switches, which demand both extremely high performance and a limited gate area, a significant adjustment of the gate etch chemistry or bias condition is usually exploited because of the need for a low gate area.
The present invention permits the use of conventional gate etch processes by placing polysilicon pads underneath probe pads during chip layout. Accordingly, the overall ratio of polysilicon to chip area can be increased so that conventional gate etching processes can be used, while the ratio of gate polysilicon to chip area can be kept small for better device operation. In addition, by increasing the polysilicon area in the chip layout, the gate etch process margin for deep sub-micron applications is improved.
In accordance with one aspect of the present invention, a semiconductor device comprises first and second polysilicon and metal pads. The first polysilicon forms circuit elements of the semiconductor device on a chip, and at least some of the circuit elements comprise polysilicon gates. The second polysilicon forms polysilicon pads of the semiconductor device on the chip. The metal pads cover the polysilicon pads.
In accordance with another aspect of the present invention, a semiconductor device chip comprises first, second, and third transistors, a plurality of polysilicon resistors, a plurality of polysilicon pads, and contacts. The first transistor comprises gate regions and alternating source and drain regions. Each gate region of the first transistor is between a pair of adjacent source and drain regions, and each gate region of the first transistor comprises polysilicon. The second transistor comprises gate regions and alternating source and drain regions. Each gate region of the second transistor is between a pair of adjacent source and drain regions, and each gate region of the second transistor comprises polysilicon. The third transistor comprises gate regions and alternating source and drain regions. Each gate region of the third transistor is between a pair of adjacent source and drain regions, and each gate region of the third transistor comprises polysilicon. The contacts cover the polysilicon pads.
In accordance with still another aspect of the present invention, a method of making an RF switch comprises forming a plurality of polysilicon gates on a chip, and forming a plurality of polysilicon pads on the chip so that there is substantially little RF coupling between the polysilicon pads and the polysilicon gates.